This invention relates to differential detection demodulators used in the radio communication systems, and more particularly to the improvements in the frequency converter and the phase comparator or the phase detection circuit used in the differential detection demodulators.
Referring to FIG. 1, a differential detection demodulator using a phase detection circuit is described. A digital differential detection demodulator using a phase detection circuit is disclosed, for example, in H. Tomita et al., "DIGITAL INTERMEDIATE FREQUENCY DEMODULATION TECHNIQUE", Paper B-299, 1990 Fall National Conference of the Institute of Electronics, Information and Communication Engineers of Japan. The differential detection demodulator is described by reference to drawings.
FIG. 1 is a block diagram showing the structure of a digital differential detection demodulator provided with a phase detection circuit. First, the received signal is supplied to a limiter amplifier 10. The output of the limiter amplifier 10 is coupled to a phase detection circuit 200 including: a counter 201 counting in modulo K, where K is a positive integer; and a D flip-flop array 202. The output of the phase detection circuit 200 is coupled to: a delay element 40 having a delay time equal to the one symbol period of the received signal; and a subtractor 41 effecting subtraction in modulo 2.pi..
Next the operation of the circuit of FIG. 1 is described. The received signal, which is a differential phase shift keying (DPSK) signal, is shaped by the limiter amplifier 10 into a rectangular waveform of constant amplitude. Namely, the limiter amplifier 10 acts as a quantizer for effecting 2-level quantization upon the received signal. Thus, the received signal is quantized by the limiter amplifier 10 into a 2-level signal taking the value either at the logical "0" or logical "1".
The counter 201 of modulo K within the phase detection circuit 200 is supplied by a clock signal having a frequency practically equal to K times the frequency of the received signal. The output of the counter 201 is supplied to the D flip-flop array 202, which is driven by the 2-level quantized received signal output from the limiter amplifier 10. The output of the phase detection circuit 200 represents the relative phase of the 2-level quantized received signal with respect to a virtual phase reference signal.
Next this is described by reference to waveform diagrams. FIGS. 2 and 3 are timing charts showing the waveforms exemplifying the operation of the phase detection circuit 200, where K=16. In FIG. 2 are shown, from top to bottom, the waveforms of: the clock supplied to the counter 201; the output of the counter 201; the virtual phase reference signal, which is obtained by dividing the clock of the counter 201 by K (equal to 16 in this case); the 2-level quantized received signal; and the output of the D flip-flop array 202. From top to bottom in FIG. 3 are shown the waveforms of: the clock for the counter 201; the output of the counter 201; the virtual phase reference signal; the 2-level quantized received signal A, the phase of which is increasingly lagged; output A of D flip-flop array 202 corresponding to the 2-level quantized received signal A; the 2-level quantized received signal B, the phase of which is increasingly led; and the output B of the D flip-flop array 202 corresponding to the 2-level quantized received signal B.
The virtual phase reference signal rises to logical "1" at the instant when the output of the counter 201 is reset to logical "0", and falls to logical "0" at the instant when the output of the counter 201 reaches K/2 (equal to 8 in this case). If the period of the clock of the counter 201 is represented by T and that of the virtual phase reference signal T.sub.r, then: EQU T.sub.r =KT
Thus, if the length of time between the rising edges of the virtual phase reference signal and the 2-level quantized received signal is represented by T, then the phase shift .psi. of the 2-level quantized received signal relative to the virtual phase reference signal is given by: EQU .psi.=2.pi..sigma./T.sub.r =2.pi..tau./(K T)
On the other hand, as seen from FIG. 2, the output of the counter 201 at the rising edge of the 2-level quantized received signal is equal to an integer obtained by dividing the time .tau. by the period T of the clock of the counter 201 and then discarding the fractional parts of the quotient.
The D flip-flop array 202 is driven at each rising edge of the 2-level quantized received signal to hold the output of the counter 201. Thus, the output of the D flip-flop array 202 is equal to the integer obtained by dividing the shift time .tau. by the period T of the clock of the counter 201 and then discarding the fractional parts of the quotient resulting from the division. Namely, if the output of the D flip-flop array 202 is represented by .mu., where .mu..epsilon.{0, 1,. . . , K-1}, then the following relation holds among .mu., T and .tau.: EQU .mu..ltoreq..tau./T&lt;(.mu.+1)
Thus, the following relation holds between the phase shift .psi. of the 2-level quantized received signal relative to the virtual phase reference signal and the output .mu. of the D flip-flop array 202: EQU 2.pi..mu./K.ltoreq..psi.&lt;2.pi.(.mu.+1)/K
This relation shows that the output of the D flip-flop array 202 can be regarded as the relative phase of the 2-level quantized received signal with respect to the virtual phase reference signal.
FIG. 2 shows the case where the relative phase of the 2-level quantized received signal with respect to the virtual phase reference signal is constant. Thus, the output of the D flip-flop array 202 remains at eight (8). On the other hand, FIG. 3 shows the case where the relative phase signal of the 2-level quantized received signal A is increasingly lagged and the relative phase of the 2-level quantized received signal B is increasingly led. Thus, upon receiving the 2-level quantized received signal A, the output A of the D flip-flop array 202 increases from seven (7) to nine (9). On the other hand, upon receiving the 2-level quantized received signal B, the output B of the D flip-flop array 202 decreases from nine (9) to seven (7). In either case, the output of the D flip-flop array 202 varies in proportion to the variation of the relative phase of the 2-level quantized received signal with respect to the virtual phase reference signal.
The phase detection circuit of FIG. 1 has the following disadvantage. The D flip-flop array 202 is driven only at the rising edges of the 2-level quantized received signal. Thus, the relative phase signal output from the phase detection circuit is updated only at each full period of the 2-level quantized received signal. In principle, however, the value of the relative phase of the 2-level quantized received signal can be updated two times for each period of the 2-level quantized received signal. Namely, the phase detection circuit of FIG. 1 has the disadvantage that the rate at which the relative phase signal is updated is low.
Next, a differential detection demodulator provided with a phase detection circuit which solves this problem of the circuit of FIG. 1 is described.